Standard wafer sizes
Silicon wafers are available in a variety of sizes from 25.4 mm (1 inch) to 300 mm (11.8 inches). Semiconductor fabrication plants (also known as fabs) are defined by the size of wafers that they are tooled to produce. The size has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab considered to be 300mm (12 inch), with the next standard set to be 450mm (18 inch). Intel, TSMC and Samsung are separately conducting research to the advent of 450mm "prototype" (research) fabs by 2012. Dean Freeman, an analyst with Gartner Inc., predicted that production fabs could emerge sometime between the 2017 and 2019 timeframe.
- 1 inch.
- 2 inch (50.8 mm). Thickness 275 µm.
- 3 inch (76.2 mm). Thickness 375 µm.
- 4 inch (100 mm). Thickness 525 µm.
- 5 inch (127 mm) or 125 mm (4.9 inch). Thickness 625 µm.
- 150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm.
- 200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm.
- 300 mm (11.8 inch, usually referred to as "12 inch" or "Pizza size" wafer). Thickness 775 µm.
- 450 mm ("18 inch"). Thickness 925 µm (expected).
Wafers grown using materials other than silicon are generally not available in sizes over 100 mm, and will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the material used; the wafer must be thick enough to support its own weight without cracking during handling. The larger the wafer, the less space on the edges as a percentage of total space. This means, less of the wafer is un-etched, and in theory should have higher productivity. This is the basis of shifting to larger and larger wafer sizes. Conversion to 300 mm wafers from 200 mm wafers began in earnest in 2000, and reduced the price per die about 30-40%. However, this was not without significant problems for the industry.
The next step to 450 mm should accomplish similar productivity gains as the previous size increase. However, machinery needed to handle and process larger wafers results in increased investment costs to build a single factory. There is considerable resistance to moving up to 450 mm by 2012 despite the obvious productivity enhancements, mainly because companies feel it would take too long to recoup their investment.[14] The difficult and costly 300 mm process only accounted for appoximately 20% of worldwide capacity on a square inches basis by the end of 2005. The step up to 300 mm required a major change from the past, with fully automated factories using 300 mm wafers versus barely automated factories for the 200 mm wafers. These major investments were undertaken in the economic downturn following the dot-com bubble, resulting in huge resistance to upgrading to 450 mm by the original timeframe.
Other initial technical problems in the ramp up to 300 mm included vibrational effects, gravitational bending (sag), and problems with flatness. Among the new problems in the ramp up to 450 mm are that the crystal ingots will be 3 times heavier (total weight a metric ton) and take 2-4 times longer to cool, and the process time will be double. All told, the development of 450 mm wafers require significant engineering, time, and cost to overcome.
Analytical die count estimation
For any given wafer diameter [d, mm] and target IC size [S, mm2], there is an exact number of integral die pieces that can be sliced out of the wafer. The gross Die Per Wafer [DPW] can be estimated by the following expression:
Note, that the gross die count does not take into account the die defect loss, various alignment markings and test sites on the wafer.
Crystalline orientation
Wafers are grown from crystal having a regular crystal structure, with silicon having a diamond cubic structure with a lattice spacing of 5.430710 Å (0.5430710 nm). When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the Miller index with or faces being the most common for silicon. Orientation is important since many of a single crystal's structural and electronic properties are highly anisotropic. Ion implantation depths depend on the wafer's crystal orientation, since each direction offers distinct paths for transport. Wafer cleavage typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("dies") so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.
Wafer flats and orientation notches
Wafers under 200 mm generally have flats cut into one or more sides indicating crystallographic planes of high symmetry (usually the{110} face) and, in old-fashioned wafers (those below about 100 mm diameter), the wafer's orientation and doping type (see illustration for conventions). Modern wafers use a notch to convey this information, in order to waste less material
Impurity doping
Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity doping concentration between 1013 and 1016 per cm3 of boron, phosphorus, arsenic, or antimony which is added to the melt and defines the wafer as either bulk n-type or p-type. However, compared with single-crystal silicon's atomic density of 5×1022 atoms per cm3, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some interstitial oxygen concentration. Carbon and metallic contamination are kept to a minimum. Transition metals, in particular, must be kept below parts per billion concentrations for electronic applications.
Compound semiconductors
While silicon is the most prevalent type of wafer used in the electronics industry, other compound III-V or II-VI type wafers have also been employed. Gallium arsenide (GaAs) wafers are one common III-V semiconductor material which can be produced using the Czochralski process.
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